dev

		<maven.compiler.target>17</maven.compiler.target>

		<build.date>${maven.build.timestamp}</build.date>

		<version>${project.version}</version>

		<skipTests>true</skipTests>

	</properties>

	<repositories>

		<repository>

		amomin_w_aq, amomin_w_rl, amomin_w, amomax_w_aqrl, amomax_w_aq, amomax_w_rl, amomax_w, amominu_w_aqrl, amominu_w_aq,

		amominu_w_rl, amominu_w, amomaxu_w_aqrl, amomaxu_w_aq, amomaxu_w_rl, amomaxu_w, lr_d_aqrl, lr_d_aq, lr_d_rl, lr_d, sc_d_aqrl,

		sc_d_aq, sc_d_rl, sc_d, amoadd_d_aqrl, amoadd_d_aq, amoadd_d_rl, amoadd_d,

		amoswap_d_aqrl, amoswap_d_aq, amoswap_d_rl, amoswap_d, amoxor_d_aqrl, amoxor_d_aq, amoxor_d_rl, amoxor_d, amoand_d_aqrl, amoand_d_aq, amoand_d_rl, amoand_d, amoor_d_aqrl, amoor_d_aq, amoor_d_rl, amoor_d, amomin_d_aqrl, amomin_d_aq, amomin_d_rl, amomin_d, amomax_d_aqrl, amomax_d_aq, amomax_d_rl, amomax_d, amominu_d_aqrl, amominu_d_aq, amominu_d_rl, amominu_d, amomaxu_d_aqrl, amomaxu_d_aq, amomaxu_d_rl, amomaxu_d, fmadd_s, fmsub_s, fnmsub_s, fnmadd_s, fmadd_d, fmsub_d, fnmsub_d, fnmadd_d, fmadd_q, fmsub_q, fnmsub_q, fnmadd_q, slli, srli, srai, lb, lh, lw, lbu, lhu, lwu, ld, addi, slti, sltiu, xori, ori, andi, flw, fld, flq, addiw, sb, sh, sw, sd, unimp, lui, auipc, jal, ret, jr, jalr, fsw, fsd, fsq, fence_i, fence, vadd_vv, vadd_vx, vadd_vi, vsub_vv, vsub_vx, vrsub_vx, vrsub_vi, vwaddu_vv, vwaddu_vx, vwadd_vv, vwadd_vx, vwsubu_vv, vwsubu_vx, vwsub_vv, vwsub_vx, vwaddu_wv, vwaddu_wx, vwsubu_wv, vwsubu_wx, vwadd_wv, vwadd_wx, vwsub_wv, vwsub_wx, vsetvli, vsetivli, vsetvl, c_addi4spn, c_fld, c_lq, c_lw, c_flw, c_ld, reserved, c_fsd, c_sq, c_sw, c_fsw, c_sd, c_nop, c_addi, c_addiw, c_li, c_addi16sp, c_lui, c_srli, c_srai, c_andi, c_sub, c_xor, c_or, c_and, c_subw, c_addw, c_j, c_beqz, c_bnez, c_slli64, c_slli, c_flwsp, c_lwsp, c_ldsp, c_ebreak, c_jr, c_mv, c_jalr, c_add, c_fsdsp, c_swsp, c_sdsp, fadd_s, fsub_s, fmul_s, fdiv_s, fsqrt_s, fsgnj_s, fmv_s, fsgnjn_s, fneg_s, fsgnjx_s, fabs_s, fmin_s, fmax_s, fcvt_w_s, fcvt_wu_s, fmv_x_w, feq_s, flt_s, fle_s, fclass_s, fcvt_s_w, fcvt_s_wu, fmv_w_x, fcvt_l_s, fcvt_lu_s, fcvt_s_l, fcvt_s_lu, fadd_d, fsub_d, fmul_d, fdiv_d, fsqrt_d, fsgnj_d, fmv_d, fsgnjn_d, fneg_d, fsgnjx_d, fabs_d, fmin_d, fmax_d, fcvt_s_d, fcvt_d_s, fmv_x_d, feq_d, flt_d, fle_d, fclass_d, fcvt_w_d, fcvt_wu_d, fmv_d_x, fcvt_l_d, fcvt_lu_d, fcvt_d_l, fcvt_d_lu, fadd_q, fsub_q, fmul_q, fdiv_q, fsqrt_q, fsgnj_q, fsgnjn_q, fsgnjx_q, fmin_q, fmax_q, fcvt_s_q, fcvt_q_s, fcvt_d_q, fcvt_q_d, feq_q, flt_q, fle_q, fclass_q, fcvt_w_q, fcvt_wu_q, fcvt_q_w, fcvt_q_wu, fcvt_l_q, fcvt_lu_q, fcvt_q_l, fcvt_q_lu, pause_sim, ecall, ebreak, sret, mret, wfi, sfence_vm, csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci, beq, bne, blt, bge, bltu, bgeu, beqz, bnez, bltz, bgtz, blez, bgez

		amoswap_d_aqrl, amoswap_d_aq, amoswap_d_rl, amoswap_d, amoxor_d_aqrl, amoxor_d_aq, amoxor_d_rl, amoxor_d, amoand_d_aqrl, amoand_d_aq, amoand_d_rl, amoand_d, amoor_d_aqrl, amoor_d_aq, amoor_d_rl, amoor_d, amomin_d_aqrl, amomin_d_aq, amomin_d_rl, amomin_d, amomax_d_aqrl, amomax_d_aq, amomax_d_rl, amomax_d, amominu_d_aqrl, amominu_d_aq, amominu_d_rl, amominu_d, amomaxu_d_aqrl, amomaxu_d_aq, amomaxu_d_rl, amomaxu_d, fmadd_s, fmsub_s, fnmsub_s, fnmadd_s, fmadd_d, fmsub_d, fnmsub_d, fnmadd_d, fmadd_q, fmsub_q, fnmsub_q, fnmadd_q, slli, srli, srai, lb, lh, lw, lbu, lhu, lwu, ld, addi, slti, sltiu, xori, ori, andi, flw, fld, flq, addiw, sb, sh, sw, sd, unimp, lui, auipc, jal, ret, jr, jalr, fsw, fsd, fsq, fence_i, fence, vadd_vv, vadd_vx, vadd_vi, vsub_vv, vsub_vx, vrsub_vx, vrsub_vi, vwaddu_vv, vwaddu_vx, vwadd_vv, vwadd_vx, vwsubu_vv, vwsubu_vx, vwsub_vv, vwsub_vx, vwaddu_wv, vwaddu_wx, vwsubu_wv, vwsubu_wx, vwadd_wv, vwadd_wx, vwsub_wv, vwsub_wx, vsetvli, vsetivli, vsetvl, c_addi4spn, c_fld, c_lq, c_lw, c_flw, c_ld, reserved, c_fsd, c_sq, c_sw, c_fsw, c_sd, c_nop, c_addi, c_addiw, c_li, c_addi16sp, c_lui, c_srli, c_srai, c_andi, c_sub, c_xor, c_or, c_and, c_subw, c_addw, c_j, c_beqz, c_bnez, c_slli64, c_slli, c_flwsp, c_fldsp, c_lwsp, c_ldsp, c_ebreak, c_jr, c_mv, c_jalr, c_add, c_fsdsp, c_swsp, c_sdsp, fadd_s, fsub_s, fmul_s, fdiv_s, fsqrt_s, fsgnj_s, fmv_s, fsgnjn_s, fneg_s, fsgnjx_s, fabs_s, fmin_s, fmax_s, fcvt_w_s, fcvt_wu_s, fmv_x_w, feq_s, flt_s, fle_s, fclass_s, fcvt_s_w, fcvt_s_wu, fmv_w_x, fcvt_l_s, fcvt_lu_s, fcvt_s_l, fcvt_s_lu, fadd_d, fsub_d, fmul_d, fdiv_d, fsqrt_d, fsgnj_d, fmv_d, fsgnjn_d, fneg_d, fsgnjx_d, fabs_d, fmin_d, fmax_d, fcvt_s_d, fcvt_d_s, fmv_x_d, feq_d, flt_d, fle_d, fclass_d, fcvt_w_d, fcvt_wu_d, fmv_d_x, fcvt_l_d, fcvt_lu_d, fcvt_d_l, fcvt_d_lu, fcvt_d_w, fcvt_d_wu, fadd_q, fsub_q, fmul_q, fdiv_q, fsqrt_q, fsgnj_q, fsgnjn_q, fsgnjx_q, fmin_q, fmax_q, fcvt_s_q, fcvt_q_s, fcvt_d_q, fcvt_q_d, feq_q, flt_q, fle_q, fclass_q, fcvt_w_q, fcvt_wu_q, fcvt_q_w, fcvt_q_wu, fcvt_l_q, fcvt_lu_q, fcvt_q_l, fcvt_q_lu, pause_sim, ecall, ebreak, sret, mret, wfi, sfence_vm, csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci, beq, bne, blt, bge, bltu, bgeu, beqz, bnez, bltz, bgtz, blez, bgez

	}

	static {

			return InstructionType.fmin_d;

		} else if (funct7 == 0b0010101 && funct3 == 1) {

			return InstructionType.fmax_d;

		} else if (funct7 == 0b1000000 && frs2 == 1) {

		} else if (funct7 == 0b0100000 && frs2 == 1) {

			return InstructionType.fcvt_s_d;

		} else if (funct7 == 0b0100001 && frs2 == 0) {

			return InstructionType.fcvt_d_s;

			return InstructionType.fcvt_l_d;

		} else if (funct7 == 0b1100001 && frs2 == 3) {

			return InstructionType.fcvt_lu_d;

		} else if (funct7 == 0b1101001 && frs2 == 0) {

			return InstructionType.fcvt_d_w;

		} else if (funct7 == 0b1101001 && frs2 == 1) {

			return InstructionType.fcvt_d_wu;

		} else if (funct7 == 0b1101001 && frs2 == 2) {

			return InstructionType.fcvt_d_l;

		} else if (funct7 == 0b1101001 && frs2 == 3) {

	public Line decodeCompressed(int arr[]) throws WrongInstructionException {

		int opcode = arr[0] & 0b11;

		int funct3 = (arr[1] & 0b11100000) >> 5;

		int value = arr[1] << 8 | arr[0];

		//int value = arr[1] << 8 | arr[0];

		String code = null;

		InstructionType ins = null;

				code = ins + " " + Registers.getRegXNum32(rd) + "," + Registers.getRegXNum32(rd) + ",0x" + Long.toHexString(imm);  //waiting to test

			}

		} else if (opcode == 2 && funct3 == 1) {

			if (rd == 0) {

				ins = InstructionType.c_flwsp;

			// funct3=001 of quadrant 2 is c.fldsp on both rv32 and rv64, and

			// it loads eight bytes. c.flwsp is funct3=011 and exists only on

			// rv32, where this slot holds c.ldsp instead, so the two are never

			// the same encoding and this one is never c.flwsp.

			ins = InstructionType.c_fldsp;

			reg_imm = getCI(arr, 3);//according the shift of imm

			rd = (int) reg_imm.get("rd");

			imm = (long) reg_imm.get("imm");

				code = ins + " " + Registers.getRegFNum32(rd) + "," + imm + "(sp)";  //waiting to test

			}

			code = ins + " " + Registers.getRegFNum32(rd) + "," + imm + "(sp)";

		} else if (opcode == 2 && funct3 == 2) {

			ins = InstructionType.c_lwsp;

			rs2 = (int) reg_imm.get("rs2");

			imm = (long) reg_imm.get("imm");

			code = ins + " " + Registers.getRegXNum32(rs2) + "," + imm + "(sp)";

			code = ins + " " + Registers.getRegFNum32(rs2) + "," + imm + "(sp)";

		} else if (opcode == 2 && funct3 == 6) {

			ins = InstructionType.c_swsp;

				ins = String.format("%s %s,%s(%s)", insName, Registers.getRegXNum32(rd), imm, Registers.getRegXNum32(rs1));

			} else if (opcode == 0b0000111) { //floating

				ins = String.format("%s %s,%s,%s", insName, Registers.getRegFNum32(rd), Registers.getRegXNum32(rs1), imm);

				System.out.println("HI");

			} else {

				ins = String.format("%s %s,%s,%s", insName, Registers.getRegXNum32(rd), Registers.getRegXNum32(rs1), imm);

			}

		if (reg == null) {

			return "0x" + Integer.toHexString(i);

		}

		return regXMap16.get(i);

		return reg;

	}

	public static String getRegXNum16(int i) {