Explore projects

Our OpenLane repo for RISC-V cpu

Build by antlr

(Deprecated) Logic simulator - for soft core cpu development

Plugin for VSCode to view vcd file produced by gtkwave

IDE for RISC-V

Java swing component to display vcd

RISC-V cpu design, first attempt

Commands to manipulate the data on Office 365

RISC-V CPU

Java library to read VCD (Value Change Dump) format file. https://en.wikipedia.org/wiki/Value_change_dump

Example for https://www.youtube.com/watch?v=qmStOgtZL-k and https://www.youtube.com/watch?v=Ilq31U9eHpo&t=4s

TheDB database

Helper library to manipulate ELF/Mach-O/PE format executable files

Extending Microsoft Office UI Fabric Library

Java library to manipulate FPGA lookup table