Explore projects

(Deprecated) Logic simulator - for soft core cpu development

Plugin for VSCode to view vcd file produced by gtkwave

IDE for RISC-V

Java swing component to display vcd

RISC-V cpu design, first attempt

Commands to manipulate the data on Office 365

Load ubc executable to run in Microsoft Windows

Helper library to manipulate ELF/Mach-O/PE format executable files

Display waveform from vcd file in wordpress https://quantr.foundation/vcd

Quantr Operating System

RISC-V CPU

Example for https://www.youtube.com/watch?v=qmStOgtZL-k and https://www.youtube.com/watch?v=Ilq31U9eHpo&t=4s

TheDB database

Java library to manipulate FPGA lookup table

Extending Microsoft Office UI Fabric Library

parse the file generated by "-d nochain,cpu -D dump.log"